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AOZ1212
EZBuckTM 3A Simple Buck Regulator
General Description
The AOZ1212 is a high ef ciency , simple to use, 3A buck regulator e xible enough to be optimized for a variety of applications. The AOZ1212 works from a 4.5V to 27V input voltage range, and provides up to 3A of continuous output current on each buck regulator output. The output voltage is adjustable down to 0.8V. The AOZ1212 comes in an SO-8 or DFN-8 package and is rated over a -40C to +85C ambient temperature range.
Features

4.5V to 27V operating input voltage range 70m internal NFET, ef ciency: up to 95% Internal soft start Output voltage adjustable down to 0.8V 3A continuous output current Fixed 370kHz PWM operation Cycle-by-cycle current limit Short-circuit protection Thermal shutdown Small size SO-8 or DFN-8 package
Applications

Point of load DC/DC conversion Set top boxes DVD drives and HDD LCD monitors & TVs Cable modems Telecom/networking/datacom equipment
Typical Application
VIN
C1 22F C7
VIN EN
BS LX
L1 6.8H
VOUT
R1
AOZ1212
VBIAS
C4
FB GND
R2
C2, C3 22F
COMP
RC CC
Figure 1. 3.3V/3A Buck Regulator
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AOZ1212
Ordering Information
Part Number
AOZ1212AI AOZ1212AI
S nt RoH plia Com
Ambient Temperature Range
-40C to +85C -40C to +85C
Package
SO-8 SO-8
Environmental
RoHS RoHS
All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
LX BST GND FB
1 2 3 4 8 7 6 5
VBIAS VIN EN COMP
LX BST GND FB
1 2 3 4
8
VIN GND DFN-8
(Top Thru View)
VBIAS VIN EN COMP
7 6 5
SO-8
(Top View)
Pin Description
Pin Number
1 2 3 4 5 6 7 8
Pin Name
LX BST GND FB COMP EN VIN VBIAS
Pin Function
PWM output connection to inductor. LX pin needs to be connected externally. Thermal connection for output stage. Bootstrap voltage input. High side driver supply. Connected to 0.1F capacitor between BST and LX. Ground. Feedback input. It is regulated to 0.8V. The FB pin is used to determine the PWM output voltage via a resistor divider between the output and GND. External loop compensation. Output of internal error ampli er . Connect a series RC network to GND for control loop compensation. Enable pin. The enable pin is active HIGH. Connect EN pin to VIN if not used. Do not leave the EN pin oating. Supply voltage input. Range from 4.5V to 27V. When VIN rises above the UVLO threshold the device starts up. All VIN pins need to be connected externally. Compensation pin of internal linear regulator. Place put a 1F capacitor between this pin and ground.
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AOZ1212
Block Diagram
VIN
+5V
VBIAS
EN
UVLO & POR
5V LDO Regulator
OTP ISen
+ -
Reference & Bias
Softstart ILimit Q1
BST
0.8V
+ -
GM = 200A/V EAmp
+ - +
FB
PWM Comp
PWM Control Logic
LX
COMP
Frequency Foldback Comparator 370kHz/24kHz Oscillator Q2
+ 0.2V -
GND
Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings may damage the device.
Recommend Operating Ratings
Rating
30V -0.7V to VIN+0.3V -0.3V to VIN+0.3V -0.3V to 6V -0.3V to 6V VLX+6V -0.3V to 6V +150C -65C to +150C 2kV
The device is not guaranteed to operate beyond the Maximum Operating Ratings.
Parameter
Supply Voltage (VIN) LX to GND EN to GND FB to GND COMP to GND BST to GND VBIAS to GND Junction Temperature (TJ) Storage Temperature (TS) ESD Rating: Human Body Model(1)
Parameter
Supply Voltage (VIN) Output Voltage Range Ambient Temperature (TA) Package Thermal Resistance (JA)(2) SO-8
Rating
4.5V to 27V 0.8V to VIN -40C to +85C 105C/W 53C/W
DFN-8
Note: 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5k in series with 100pF.
Note: 2. The value of JA is measured with the device mounted on 1-in2 FR-4 board with 2oz. Copper, in a still air environment with TA = 25C. The value in any given application depends on the user's speci c board design.
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AOZ1212
TA = 25C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified(3)
Electrical Characteristics
Symbol
VIN VUVLO IIN IOFF VFB Supply Voltage
Parameter
Input Under-Voltage Lockout Threshold Supply Current (Quiescent) Shutdown Supply Current Feedback Voltage Load Regulation Line Regulation VIN Rising VIN Falling
Conditions
Min.
4.5
Typ.
4.3 4.1 2 3
Max.
27
Units
V V
IOUT = 0, VFB = 1.2V, VEN > 2V VEN = 0V 0.782
3 20 0.818
mA A V % %/V
0.8 0.5 0.08
IFB ENABLE VEN VHYS
Feedback Voltage Input Current EN Input Threshold EN Input Hysteresis Off Threshold On Threshold
200 0.6 2.5 200
nA
V mV
MODULATOR fO DMAX DMIN GVEA GEA ILIM Frequency Maximum Duty Cycle Minimum Duty Cycle Error Ampli er Voltage Gain Error Ampli er Transconductance Current Limit Over-Temperature Shutdown Limit fSC tSS RDS(ON) Short Circuit Hiccup Frequency Soft Start Interval High-Side Switch On-Resistance High-Side Switch Leakage VEN = 0V, VLX = 0V TJ Rising TJ Falling VFB = 0V 3.5 145 100 24 6 4 70 100 10 500 200 5.0 315 85 6 370 425 kHz % % V/V A / V A C kHz ms m A
PROTECTION
PWM OUTPUT STAGE
Note: 3. Speci cation in BOLD indicate an ambient temperature range of -40C to +85C. These speci cations are guar anteed by design.
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AOZ1212
Circuit of Figure 1. TA = 25C, VIN = VEN = 24V, VOUT = 3.3V unless otherwise speci ed.
Typical Performance Characteristics
Light Load (DCM) Operation
Full Load (CCM) Operation
Vin ripple 0.1V/div Vo ripple 20mV/div IL 1A/div VLX 20V/div Vin ripple 0.1V/div Vo ripple 20mV/div IL 1A/div VLX 20V/div
1s/div
1s/div
Startup to Full Load
Short Circuit Protection
Vo 2V/div
Vo 2V/div
lin 0.5A/div
lL 2A/div
2ms/div
200s/div
50% to 100% Load Transient
Short Circuit Recovery
Vo Ripple 200mV/div
Vo 2V/div
lo 1A/div
IL 2A/div
200s/div
2ms/div
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AOZ1212
Efficiency Curves
Efficiency
100 95 Efficieny (%) 90 85 80 75 0.2
1.8V OUTPUT
VIN = 5V
Efficiency
100 95 Efficieny (%) 90 85 80 75 0.2
5.0V OUTPUT 3.3V OUTPUT
VIN = 12V
8.0V OUTPUT 3.3V OUTPUT
0.5 0.8
1.1
1.4 1.7
2.0 2.3
2.6
2.9
3.2
0.5 0.8
1.1
1.4 1.7
2.0 2.3
2.6
2.9
3.2
Current (A)
Current (A)
Efficiency
100 95
8.0V OUTPUT
VIN = 24V
Efficieny (%)
90
5.0V OUTPUT
85
3.3V OUTPUT
80 75
0.2
0.5 0.8
1.1
1.4 1.7 2.0 2.3 Current (A)
2.6
2.9
3.2
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AOZ1212
Detailed Description
The AOZ1212 is a current-mode step down regulator with integrated high side NMOS switch. It operates from a 4.5V to 27V input voltage range and supplies up to 3A of load current. The duty cycle can be adjusted from 6% to 85% allowing a wide range of output voltages. Features include; enable control, Power-On Reset, input under voltage lockout, x ed internal soft-start and thermal shut down. The AOZ1212 is available in an SO-8 or DFN-8 package. high-side switch is off. The inductor current is freewheeling through the Schottky diode to the output.
Switching Frequency
The AOZ1212 switching frequency is x ed and set by an internal oscillator. The switching frequency is set to 370kHz.
Output Voltage Programming
Output voltage can be set by feeding back the output to the FB pin with a resistor divider network. In the application circuit shown in Figure 1. The resistor divider network includes R1 and R2. Typically, a design is started by picking a x ed R2 value and calculating the required R1 value with equation below.
Enable and Soft Start
The AOZ1212 has an internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to the regulation voltage. A soft start process begins when the input voltage rises to 4.1V and voltage on EN pin is HIGH. In the soft start process, the output voltage is typically ramped to regulation voltage in 6.8ms. The 6.8ms soft start time is set internally. If the enable function is not used, connect the EN pin to VIN. Pulling EN to ground will disable the AOZ1212. Do not leave EN open. The voltage on the EN pin must be above 2.5 V to enable the AOZ1212. When voltage on EN pin falls below 0.6V, the AOZ1212 is disabled. If an application circuit requires the AOZ1212 to be disabled, an open drain or open collector circuit should be used to interface with the EN pin.
R 1 V O = 0.8 x 1 + ------ R 2
Some standard values for R1 and R2 for the most commonly used output voltages are listed in Table 1. Table 1. VO (V)
0.8 1.2 1.5 1.8 2.5 3.3 5.0 1.0 4.99 10 12.7 21.5 31.6 52.3
R1 (k)
10 11.5 10.2 10 10 10
R2 (k)
Open
Steady-State Operation
Under steady-state conditions, the converter operates in x ed frequency and Continuous-Conduction Mode (CCM). The AOZ1212 integrates an internal N-MOSFET as the high-side switch. Inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power MOSFET. Since the N-MOSFET requires a gate voltage higher than the input voltage, a boost capacitor connected between the LX and BST pins drives the gate. The boost capacitor is charged while LX is low. An internal 10 switch from LX to GND is used to ensure that LX is pulled to GND even in the light load. Output voltage is divided down by the external voltage divider at the FB pin. The difference of the FB pin voltage and reference is ampli ed b y the internal transconductance error ampli er . The error voltage, which shows on the COMP pin, is compared against the current signal. The current signal is the sum of inductor current signal and ramp compensation signal, at the PWM comparator input. If the current signal is less than the error voltage, the internal high-side switch is on. The inductor current o ws from the input through the inductor to the output. When the current signal exceeds the error voltage, the
Rev. 1.1 October 2007
The combination of R1 and R2 should be large enough to avoid drawing excessive current from the output, which will cause power loss.
Protection Features
The AOZ1212 has multiple protection features to prevent system circuit damage under abnormal conditions. Over Current Protection (OCP) The sensed inductor current signal is also used for over current protection. Since the AOZ1212 employs peak current mode control, the COMP pin voltage is proportional to the peak inductor current. The COMP pin voltage is limited to be between 0.4V and 2.5V internally. The peak inductor current is automatically limited cycle by cycle.
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AOZ1212
The cycle-by-cycle current limit threshold is internally set. When the load current reaches the current limit threshold, the cycle-by-cycle current limit circuit turns off the high side switch immediately to terminate the current duty cycle. The inductor current stops rising. The cycleby-cycle current limit protection directly limits inductor peak current. The average inductor current is also limited due to the limitation on the peak inductor current. When cycle-by-cycle current limit circuit is triggered, the output voltage drops as the duty cycle decreases. The AOZ1212 has internal short circuit protection to protect itself from catastrophic failure under output short circuit conditions. The FB pin voltage is proportional to the output voltage. Whenever the FB pin voltage is below 0.2V, the short circuit protection circuit is triggered. To prevent current limit running away when the comp pin voltage is higher than 2.1V, the short circuit protection is also triggered. As a result, the converter is shut down and hiccups at a frequency equals to 1/16 of normal switching frequency. The converter will start up via a soft start once the short circuit condition is resolved. In short circuit protection mode, the inductor average current is greatly reduced because of the low hiccup frequency. Power-On Reset (POR) A power-on reset circuit monitors the input voltage. When the input voltage exceeds 4.3V, the converter starts operation. When input voltage falls below 4.1V, the converter will stop switching. Thermal Protection An internal temperature sensor monitors the junction temperature. It shuts down the internal control circuit and high side NMOS if the junction temperature exceeds 145C. The regulator will restart automatically under the control of soft-start circuit when the junction temperature decreases to 100C. Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. For a buck circuit, the RMS value of input capacitor current can be calculated by:
VO VO I CIN _RMS = I O x --------- 1 - --------- V IN V IN
if let m equal the conversion ratio:
VO --------- = m V IN
The relationship between the input capacitor RMS current and voltage conversion ratio is calculated and shown in Figure 2. It can be seen that when VO is half of VIN, CIN is under the worst current stress. The worst current stress on CIN is 0.5 x IO.
0.5 0.4 ICIN_RMS(m) 0.3 IO 0.2 0.1 0 0 0.5 m 1
Figure 2. ICIN vs. Voltage Conversion Ratio
Application Information
The basic AOZ1212 application circuit is shown in Figure 1. Component selection is explained below. Input Capacitor The input capacitor (C1 in Figure 1) must be connected to the VIN pin and GND pin of the AOZ1212 to maintain steady input voltage and lter out the pulsing input current. The voltage rating of the input capacitor must be greater than maximum input voltage + ripple voltage. The input ripple voltage can be approximated by equation below:
For reliable operation and best performance, the input capacitors must have a current rating higher than ICIN_RMS at the worst operating conditions. Ceramic capacitors are preferred for input capacitors because of their low ESR and high ripple current rating. Depending on the application circuits, other low ESR tantalum capacitor or aluminum electrolytic capacitor may also be used. When selecting ceramic capacitors, X5R or X7R type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. Note that the ripple current rating from capacitor manufactures is based on certain amount of life time. Further de-rating may be necessary for practical design requirement. Inductor The inductor is used to supply constant current to output when it is driven by a switching voltage. For given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is,
IO VO VO V IN = ------------------ x 1 - --------- x --------V IN V IN f x C IN
Rev. 1.1 October 2007
VO VO I L = ----------- x 1 - --------- V IN f xL
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AOZ1212
The peak inductor current is:
I L I Lpeak = I O + -------2
High inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through inductor and switches, which results in less conduction loss. When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. The inductor takes the highest current in a buck circuit. The conduction loss on inductor needs to be checked for thermal and ef ciency requirements . Surface mount inductors in different shape and styles are available from Coilcraft, Elytone and Murata. Shielded inductors are small and radiate less EMI noise. But they cost more than unshielded inductors. The choice depends on EMI requirement, price and size. Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage speci cation and ripple current rating. The selected output capacitor must have a higher rated voltage speci cation than the maxim um desired output voltage including ripple. De-rating needs to be considered for long term reliability. Output ripple voltage speci cation is another impor tant factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below:
If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simpli ed to:
V O = I L x ES R CO
For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum capacitor or aluminum electrolytic capacitor may also be used as output capacitors. In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by:
I L I CO _RMS = ---------12
Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. Schottky Diode Selection The external freewheeling diode supplies the current to the inductor when the high side NMOS switch is off. To reduce the losses due to the forward voltage drop and recovery of diode, a Schottky diode is recommended. The maximum reverse voltage rating of the chosen Schottky diode should be greater than the maximum input voltage, and the current rating should be greater than the maximum load current.
Loop Compensation
The AOZ1212 employs peak current mode control for easy use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C lter . It greatly simpli es the compensation loop design. With peak current mode control, the buck power stage can be simpli ed to be a one-pole and one-z ero system in frequency domain. The pole is the dominant pole and can be calculated by:
1 V O = I L x ES R CO + -------------------------- 8 x f x C O
where; CO is output capacitor value and ESRCO is the Equivalent Series Resistor of output capacitor.
When low ESR ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simpli ed to:
1 V O = I L x -------------------------- 8 x f x C -
O
1 f p1 = ----------------------------------2 x C O x R L
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AOZ1212
The zero is a ESR zero due to output capacitor and its ESR. It is can be calculated by: The strategy for choosing RC and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calculate RC:
1 f Z 1 = ------------------------------------------------2 x C O x ESR CO
where; CO is the output lter capacitor , RL is load resistor value, and ESRCO is the equivalent series resistance of output capacitor.
2 x C O VO R C = f C x ----------- x ----------------------------V G xG
FB EA CS where; fC is desired crossover frequency, GEA is the error ampli er tr ansconductance, which is 200x10-6 A/V, and GCS is the current sense circuit transconductance, which is 5.64 A/V VFB is 0.8V,
The compensation design is actually to shape the converter close loop transfer function to get desired gain and phase. Several different types of compensation network can be used for AOZ1212. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. In the AOZ1212, FB pin and COMP pin are the inverting input and the output of internal transconductance error ampli er . A series R and C compensation network connected to COMP provides one pole and one zero. The pole is:
The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fp1 but lower than 1/5 of the selected crossover frequency. CC can is selected by:
1.5 C C = -----------------------------------2 x R C x f p1
The equation above can also be simpli ed to:
G EA f p2 = -----------------------------------------2 x C C x G VEA
where; GEA is the error ampli er tr ansconductance, which is 200 x 10-6 A/V, GVEA is the error ampli er v oltage
CO x RL C C = ---------------------RC
An easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com.
The zero given by the external compensation network, capacitor CC (C5 in Figure 1) and resistor RC (R1 in Figure 1), is located at:
Thermal Management and Layout Consideration
In the AOZ1212 buck regulator circuit, high pulsing current o ws through two circuit loops. The rst loop starts from the input capacitors, to the VIN pin, to the LX pins, to the lter inductor , to the output capacitor and load, and then returns to the input capacitor through ground. Current o ws in the rst loop when the high side switch is on. The second loop starts from inductor, to the output capacitors and load, to the GND pin of the AOZ1212, to the LX pins of the AZO1212. Current o ws in the second loop when the low side diode is on. In PCB layout, minimizing the two loops area reduces the noise of this circuit and improves ef ciency . A ground plane is recommended to connect input capacitor, output capacitor, and GND pin of the AOZ1212. In the AOZ1212 buck regulator circuit, the three major power dissipating components are the AOZ1212, external diode and output inductor. The total power
1 f Z 2 = -----------------------------------2 x C C x R C
To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where the control loop has unity gain. The crossover frequency is also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high due to system stability concern. When designing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be less than 1/10 of switching frequency. It is recommended to choose a crossover frequency less than 30kHz.
f C = 30kHz
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AOZ1212
dissipation of converter circuit can be measured by input power minus output power. Several layout tips are listed below for the best electric and thermal performance. Figure 3a and Figure 3b show layout examples for the AOZ1212A and AOZ1212D respectively. 1. Do not use thermal relief connection to the VIN and the GND pin. Pour a maximized copper area to the GND pin and the VIN pin to help thermal dissipation. 2. Input capacitor should be connected as close as possible to the VIN and GND pins. 3. Make the current trace from LX pins to L to CO to GND as short as possible. 4. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. 5. Keep sensitive signal traces such as the trace connecting FB and COMP pins away from the LX pins.
P total _loss = V IN x I IN - V O x I O
The power dissipation of inductor can be approximately calculated by output current and DCR of the inductor.
P inductor _loss = IO2 x R inductor x 1.1
The power dissipation of the diode is:
VO P diode_loss = I O x V F x 1 - --------- V IN
The actual AOZ1212 junction temperature can be calculated with power dissipation in the AOZ1212 and thermal impedance from junction to ambient.
T junction = ( P total _loss - P inductor _loss ) x JA + + T ambient
The maximum junction temperature of AOZ1212 is 145C, which limits the maximum load current capability. The thermal performance of the AOZ1212 is strongly affected by the PCB layout. Care should be taken by users during design process to ensure that the IC will operate under the recommended environmental conditions.
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AOZ1212
C1
Cc
Rc
5 COMP 6 EN 7 Vin 8 VBIAS
C4
AOZ1212
4 FB 3 GND 2 BST 1 LX
R1
VIN
Cb
R2
L1
Vo
C2
C 2
Figure 3a. Layout Example for AOZ1212AI
Cc
Rc
AOZ1212
5 4
R1
COMP
FB GND BST LX
Cb
GND EN 6 Vin 7
3 2 1
Vin
C1
VBIAS 8
C4
R2
L1
Vo
C2
C 2
Figure 3a. Layout Example for AOZ1212DI
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AOZ1212
Package Dimensions, SO-8
D e 8 L Gauge Plane Seating Plane 0.25
E
E1
h x 45 1 7 (4x) C
0.1
A2 A
b
A1
Dimensions in millimeters
2.20 Symbols A A1 A2 b c D E1 e E h L Min. 1.35 0.10 1.25 0.31 0.17 4.80 3.80 Nom. 1.65 -- 1.50 -- -- 4.90 3.90 1.27 BSC 5.80 6.00 0.25 -- 0.40 -- 0 -- Max. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8
Dimensions in inches
Symbols A A1 A2 b c D E1 e E h L Min. 0.053 0.004 0.049 0.012 0.007 0.189 0.150 Nom. Max. 0.065 0.069 -- 0.010 0.059 0.065 -- 0.020 -- 0.010 0.193 0.197 0.154 0.157 0.050 BSC 0.228 0.236 0.244 0.010 -- 0.020 0.016 -- 0.050 0 -- 8
5.74
1.27
Unit: mm
0.80
Notes: 1. All dimensions are in millimeters. 2. Dimensions are inclusive of plating 3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils. 4. Dimension L is measured in gauge plane. 5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
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AOZ1212
Tape and Reel Dimensions, SO-8
SO-8 Carrier Tape
D1 T See Note 5 E1 E2 E P1 P2 See Note 3
B0 K0 Unit: mm Package SO-8 (12mm) A0 6.40 0.10 B0 5.20 0.10 K0 2.10 0.10 D0 1.60 0.10 D1 1.50 0.10 E 12.00 0.10 E1 1.75 0.10 E2 5.50 0.10 P0 8.00 0.10 A0 D0 P0
See Note 3
Feeding Direction P1 4.00 0.10 P2 2.00 0.10 T 0.25 0.10
SO-8 Reel
W1
G M N
S
V R
K
H W W N Tape Size Reel Size M 12mm o330 o330.00 o97.00 13.00 0.10 0.30 0.50 W1 17.40 1.00 K H 10.60 o13.00 +0.50/-0.20 S 2.00 0.50 G -- R -- V --
SO-8 Tape
Leader/Trailer & Orientation
Trailer Tape 300mm min. or 75 empty pockets
Components Tape Orientation in Pocket
Leader Tape 500mm min. or 125 empty pockets
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AOZ1212
Package Dimensions, DFN 5x4
TOP VIEW
BOTTOM VIEW
FRONT VIEW
Dimensions in millimeters
RECOMMENDED LAND PATTERN
Symbols A A3 b D D2 D3 E E2 e L L1 L2 L3 aaa bbb ccc Min. 0.70 0.40 4.90 2.05 1.66 3.90 2.23 0.50 -- Nom. 0.75 Max. 0.80
Dimensions in inches
Symbols A A3 b D D2 D3 E E2 e L L1 L2 L3 aaa bbb ccc ddd eee Min. 0.028 0.016 0.190 0.080 0.064 0.154 0.088 0.020 -- Nom. 0.30 Max. 0.032
0.20 Ref. 0.45 0.50 5.00 5.10 2.15 1.76 2.25 1.88
0.008 Ref. 0.018 0.020 0.200 0.210 0.085 0.070 0.089 0.074
4.00 4.10 2.33 2.43 0.95 BSC 0.55 0.40 0.285 Ref. 0.835 Ref. 0.15 0.10 0.10 0.08 0.05 0.60 --
0.157 0.161 0.092 0.095 0.037 BSC 0.022 0.016 0.011 0.033 0.006 0.004 0.004 0.003 0.002 0.024 --
Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters.
ddd eee
3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002. 4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. Coplanarity applies to the terminals and all other bottom surface metallization. 6. Drawing shown are for illustration only. 7. The dimensions with * are just for reference 8. Pin #3 and Pin #7 are fused to DAP.
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AOZ1212
Tape and Reel Dimensions, 5x4 DFN-8
Tape
T D1 E1
R0
.40
20 0.
E2 E B0
D0 Feeding Direction
K0
UNIT: mm
P0
A0
Package DFN 5x4 (12 mm)
A0 5.30 0.10
B0 4.30 0.10
K0 1.20 0.10
D0 1.50 Min. Typ.
D1 1.50
+0.10 / -0
E 12.00 0.30
E1 1.75 0.10
E2 5.50 0.10
P0 8.00 0.10
P1 4.00 0.20
P2 2.00 0.10
T 0.30 0.05
Leader/Trailer and Orientation
Trailer Tape 300mm Min.
Components Tape Orientation in Pocket
Leader Tape 500mm Min.
Rev. 1.1 October 2007
www.aosmd.com
Page 16 of 19
AOZ1212
II
I
R1
R1 59
Reel
M
21
6.01
R1 27
R1
Zoom In
I
R6
P
5 R5
B
W1
Zoom In
III
Tape Size 12mm
Reel Size o330
M o330
+0.3 -4.0
W1 12.40
+2.0 -0.0
B 2.40 0.3
P 0.5
0.05
3-1.8
Zoom In
/8" 3-o1
II
/4
3-
1.8 6.450.05 6.2 8.90.1 14 REF
1.8
o9
6
0.2
0.
05
3-
o1
o2
A
.9
"
N=o1002
AA
6.0
8.00 2.20
0.00 -0.05
R1
o2
1.
20
o13.0 0
0 o90.0
5.0
2.00
o17.0
R1.10 R3.10
11.90
C
1.8 12 REF
o86 .00 .1
10
41.5 REF 43.00 44.50.1 6.50
R0.5
46.00.1 44.50.1 3.3
.95
R3
4.0 6.10 40
38
EF
10.0
3/ 16
A
8R
VIEW: C
3-
2.00 6.50 10.71
o3
3o
/1
8.00.1
6"
0.80 3.00 8.000.00
+0.05
2.5 1.80
R4
"
6
Rev. 1.1 October 2007
www.aosmd.com
Page 17 of 19
AOZ1212
AOZ1212 Package Marking
AOZ1212AI
Z1212AI FAYWLT
Part Number
Fab & Assembly Location Year & Week Code
Assembly Lot Code
AOZ1212DI
Z1212DI FAYWLT
Part Number
Fab & Assembly Location Year & Week Code
Assembly Lot Code
Rev. 1.1 October 2007
www.aosmd.com
Page 18 of 19
AOZ1212
This datasheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi cant injur y of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Rev. 1.1 October 2007
www.aosmd.com
Page 19 of 19

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